Minch, Bradley Arthur (1997) Analysis, synthesis, and implementation of networks of multipleinput translinear elements. Dissertation (Ph.D.), California Institute of Technology. http://resolver.caltech.edu/CaltechETD:etd01162008075623
Abstract
At the time of its invention in the seventeenth century, the logarithmic slide rule literally revolutionized the way calculation was done. From then until the advent of the pocket calculator, this analog computational device was widely used to perform multiplications and divisions, to raise numbers to fixed powers and extract fixed roots of numbers. Today, the slide rule may be gone, but it is not forgotten. In this thesis, I present a class of simple translinear network circuits which essentially function as electronic slide rules, accurately computing products, quotients, powers, and roots. I describe two different analysis procedures that allow us to determine the steadystate relationship between input and output currents. I also describe systematic techniques for synthesizing such circuits whereby we can produce a circuit whose steadystate transfer characteristics embody some desired productofpowerlaw relationship between input and output currents. These circuits are made from multipleinput translinear elements; such elements produce output currents that are proportional to the exponential of a weighted sum of their input voltages. We can implement the weighted voltage summations with either resistive or capacitive voltage dividers. We can obtain the required exponential voltagetocurrent transformations from either bipolar transistors or subthreshold MOS transistors. The subthreshold floatinggate MOS transistor naturally implements the exponentialofaweightedsum operation in a single device. I will present experimental results from several of these translinear network circuits breadboarded from subthreshold floatinggate MOS transistors. I will also describe and present experimental data from a variety of other implementations of the multipleinput translinear element.
Item Type:  Thesis (Dissertation (Ph.D.)) 

Degree Grantor:  California Institute of Technology 
Major Option:  Computation and Neural Systems 
Thesis Committee: 

Defense Date:  20 May 1997 
Record Number:  etd01162008075623 
Persistent URL:  http://resolver.caltech.edu/CaltechETD:etd01162008075623 
Default Usage Policy:  No commercial reproduction, distribution, display or performance rights in this work are provided. 
ID Code:  199 
Collection:  CaltechTHESES 
Deposited By:  Imported from ETDdb 
Deposited On:  13 Feb 2008 
Last Modified:  25 Dec 2012 14:58 
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